In this question you are asked to design a synthesizable ALU in Verilog. This ALU gets two 9-bit signed inputs (A B) in 2’s complement format and a 4-bit select input (S) based on which decides about the operation that should be executed. The output is Q and you determine the number of bits for Q in order to have a correct answer. What follows shows these operations: If S=0 Addition (i.e. A+B) If S=1 Subtraction (A-B) If S=2 Multiplication (only the least 8 significant bits are shown in output) If S=3 Shift B to the right A times (and add 0 from right side) If S=4 Rotate B to the left A times If S=5 A is ored with B If S=6 A is anded with B If S=7 A is nanded with B If S=8 A is xnored (the logical opposite of XOR like NAND to AND) with B If S=9 complement of B is computed a. Design this ALU similar the example we did in class. First write a verilog module for each operation and then instantiate them in Top.v. Make sure you first test and verify the functionality of each submodule and then test Top.v with different inputs. b. Write testbench for the addition subtraction multiplication shifts rotate and complement Modules. Test with all extreme cases (e.g. all zero inputs all one inputs all positive inputs all negative inputs negative and positive inputs). c. Write testbench top.v top_tb and test with all extreme cases (e.g. all zero inputs all one inputs all positive inputs all negative inputs negative and positive inputs). 2 3. Reconsider question 2 with the assumption that the output is a registered output i.e. Q is loaded by the rising edge of the clock signal when reset is not active (RESET=0). Build the following: A) Consider a synchronous resetting mechanism (RESET only acts in the rising edge of the CLK signal). Implement the circuit using a sequential case statement. B) Consider an asynchronous resetting mechanism (RESET triggers a reset immediately not only on the clock signal). Implement the circuit using a sequential case statement. Note: The only difference between part A and B is the reset mechanism not the registered output. Test and verify the results with a test bench top_tb.v similar to the question 2. Requirements: Appropriate | .doc file ‘
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